1. Field of the Invention
The present invention relates to semiconductor processes for fabricating bipolar junction transistors, and more particularly to those processes for creating self-aligned, dual-base bipolar junction transistors and other bipolar junction transistor types on the same integrated circuit.
2. Description of the Related Art
The fabrication of self-aligned bipolar transistors is well known. To fabricate such a device, a single opening is usually cut through an oxide overlying an epitaxial layer, and multiple base implants (e.g., one deep and one shallow) are performed through the same opening. While such bipolar devices are well known, they are usually optimized for low voltage, high performance use, and all the bipolar junction transistors on the same integrated circuit (IC) usually are processed identically.
However, many attractive markets exist which require an integrated circuit to tolerate rather high voltages (e.g., 100-150 volts), and yet require the integrated circuit to be relatively high in performance. For example, subscriber circuits for telecommunications applications must withstand the ringing voltage associated with legacy telephone local loops, but are looked upon to support increasingly faster data rates as digital transmission techniques become more and more pervasive. Consequently, a simple, cost-effective semiconductor process is desired which provides high-voltage bipolar transistors having a high collector-to-emitter breakdown voltage and other bipolar transistors having a high forward gain.
A semiconductor process is disclosed which forms openings in a dielectric layer through which are formed features of two transistor types. In one embodiment of the invention in which both high-voltage and high-gain bipolar transistors are formed on the same integrated circuit, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, the patterned photoresist is removed and then the implant is diffused to a suitable depth. By removing the patterned photoresist, additional openings are exposed for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques. Since the two base implants for each high-voltage transistor are self-aligned to a single opening through the dielectric layer, excellent control and repeatability is achieved for the high-voltage transistors. Moreover, since the second base implant is common to both types of transistors, many of the characteristics of the two types of transistors are well matched to each other.
The characteristics of the deep base preferably provide a less steep junction with a larger radius of curvature to raise the junction breakdown voltage and therefore the BVCEO of the high-voltage bipolar junction transistors. The shallow base may be optimized for forward DC current gain (Beta) of the high gain bipolar junction transistor. Since the shallow implant is also performed into the high-voltage device, the gain of the high-voltage device is affected as well, thus improving the matching between the two transistor types. Advantageously, a single hard oxide mask controls the critical dimensions (CD""s) for both transistor types, and requires only loose CD and alignment control of the selective (i.e., 1st) base mask. The advantages of two bipolar junction transistor types are gained, yet require only the addition of a single, non-critical mask patterned only in photoresist. Additional masking steps may be used to selectively perform other diffusions or implants or to selectively mask the second base implant to create additional devices such as, for example, resistors.
In one embodiment of the invention suitable for a semiconductor fabrication process, a method for forming both first and second vertical bipolar junction transistor types includes providing a semiconductor substrate having a first polarity, forming a first dielectric layer upon the substrate, forming first and second pluralities of openings through the first dielectric layer respectively corresponding to the first and second transistor types, introducing a first dopant of a second polarity opposite that of the first polarity through the first plurality of openings to form a first doped layer within the semiconductor substrate therebelow while protecting the second plurality of openings, and introducing a second dopant of the second polarity through the second plurality of openings to form a second doped layer within the semiconductor substrate therebelow.
A semiconductor integrated circuit structure embodiment of the invention includes first and second vertical bipolar junction transistor types. The structure includes a semiconductor substrate of a first polarity having a top surface, and a first dielectric layer upon the top surface of the substrate, having first and second pluralities of openings therethrough respectively corresponding to the first and second transistor types. The structure further includes a first plurality of doped layers at the top surface of and within the substrate, each comprising a first dopant of a second polarity opposite that of the first polarity, each formed generally below and substantially aligned to a respective one of both the first and second plurality of openings within the first dielectric layer. The structure still further includes a second plurality of doped layers at the top surface of and within the substrate, each comprising a second dopant of the second polarity, each formed generally below and substantially aligned to a respective one of the second plurality of openings within the first dielectric layer.
Another semiconductor integrated circuit structure embodiment of the invention includes first and second vertical bipolar junction transistor types. The structure includes a semiconductor substrate of a first polarity having a top surface, respective isolated regions of the substrate forming respective collector nodes for the first and second vertical bipolar junction transistor types. The structure further includes a first base region formed within the substrate and substantially aligned to a first opening through a first dielectric layer overlying the first base region, the first base region corresponding to the first vertical bipolar junction transistor type and comprising a first doping profile of a second polarity opposite the first polarity. The structure still further includes a second base region formed within the substrate and substantially aligned to a second opening through the first dielectric layer overlying the second base region, the second base region corresponding to the second vertical bipolar junction transistor type and comprising a second doping profile of the second polarity.
In yet another embodiment of the present invention, a semiconductor integrated circuit structure includes a semiconductor substrate of a first polarity having a top surface, respective isolated regions of the substrate forming respective collector nodes for the first and second vertical bipolar junction transistor types. The structure includes a first base region formed within the substrate and substantially aligned to a first opening through a first dielectric layer overlying the first base region, the first base region corresponding to the first vertical bipolar junction transistor type and comprising a first doping profile of a second polarity opposite the first polarity. The structure further includes a second base region formed within the substrate and substantially aligned to a second opening through the first dielectric layer overlying the second base region, the second base region corresponding to the second vertical bipolar junction transistor type and comprising both the first doping profile and a second doping profile of the second polarity, both substantially aligned to the second opening through the first dielectric layer. The structure still further includes a first emitter region formed within the first base region at the surface of the substrate, the first emitter region comprising a third doping profile of the first polarity, and a second emitter region formed within the second base region at the surface of the substrate, the second emitter region comprising the third doping profile, wherein the first doping profile has a depth which is substantially greater than that of the second doping profile.
The present invention may be better understood, and its numerous features and advantages made even more apparent to those skilled in the art by referencing the detailed description and accompanying drawings of the embodiments described below. These and other embodiments of the present invention are defined by the claims appended hereto.